This invention relates to a semiconductor non-volatile memory device such as, for example, an electrically erasable and programmable read only memory device and, more particularly, to a split gate type memory cell of the semiconductor non-volatile memory device and a process of fabrication thereof.
A stacked gate type memory transistor is a typical example of a semiconductor non-volatile memory transistor. The stacked gate type memory transistor has a floating gate over a channel region between the source/drain regions, and a gate insulting layer and a control gate are laminated on the floating gate. The stacked gate type memory transistor stores a data bit in the form of accumulated electrons injected into the floating gate electrode. If the electrons are injected into the floating gate electrode, the accumulated electrons induce holes in the channel region, and make the threshold of the stacked gate type memory transistor high. As a result, the stacked type memory transistor does not turn on under application of a read voltage to the control electrode. On the other hand, when the accumulated electrons are evacuated from the floating gate electrode, the threshold is lowered, and the read voltage causes the stacked type memory transistor to turn on. Thus, the stacked type memory transistor takes two kinds of state depending upon the amount of accumulated electrons, and two logic levels of a data bit are respectively corresponding to the two kinds of state. In the following description, one of the two kinds of state accumulating a large amount of electrons and the other kinds of state accumulating a small amount of electrons are hereinbelow referred to as xe2x80x9cwrite-in statexe2x80x9d and xe2x80x9cerased statexe2x80x9d, respectively.
The stacked gate type memory transistor is connected in series to a standard field effect transistor, and form in combination a split gate type non-volatile memory cell. The split gate type non-volatile memory cell is effective against over-erased state. If the accumulated electrons are excessively erased from the floating gate electrode, the stacked gate type memory transistor enters into the depletion state, and is not appropriate to store a data bit. The split gate type memory cell is well known to a person skilled in the art, and no further description is incorporated hereinbelow.
The split gate type memory cell is fabricated as follows. FIGS. 1A to 1E illustrate the prior art process for fabricating the split gate type memory cell. FIG. 1E shows the structure along a cross section perpendicular to the cross section for FIGS. 1A to 1D. The process starts with preparation of a p-type silicon substrate 1. Boron is ion implanted into a certain area assigned to the split gate type memory cells at dosage of 3E13 atom/square-cm for adjusting channel dopant concentration to a target value, and, thereafter, arsenic is selectively ion implanted into the area for forming striped impurity regions 2a/2b as shown in FIG. 1A. The striped impurity regions 2a/2b serve as digital lines, and parts of the digit line serve as n-type source/drain regions of a split gate type memory cell.
Silicon oxide is deposited over the entire surface of the p-type silicon substrate 1 by using a chemical vapor deposition, and the silicon oxide layer is selectively etched away in order to expose active areas of the p-type silicon substrate 1. The remaining silicon oxide layer serves as an isolating oxide layer 3 (see FIG. 2).
Subsequently, the active areas are thermally oxidized, and a silicon oxide layer is grown to 20 nanometers thick on the active areas. Polysilicon is deposited over the entire surface of the resultant semiconductor structure, and a photo-resist etching mask (not shown) is provided on the polysilicon layer through photo-lithographic techniques. Using the photo-resist etching mask, the polysilicon layer and the silicon oxide layer are selectively etched away, and lower gate oxide layers 4 and floating gate electrodes 5 are formed on the active areas as shown in FIG. 1B. Each of the striped impurity regions 2a/2b is partially overlapped with the lower gate insulating layer 4, which is spaced from the other striped impurity region 2b/2a. 
Subsequently, silicon oxide is deposited to 20 nanometers thick over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition, and forms a silicon oxide layer 6. The resultant semiconductor structure is heated so that a silicon oxide layer 7 is grown to 20 to 30 nanometers thick on the entire surfaces of the floating gate electrodes 5 and the active areas between the floating gate electrodes 5. The polysilicon is oxidized half as fast again as the single crystal silicon, and, for this reason, the silicon oxide layer 7 on the floating gate electrodes 5 is half as thick again as the silicon oxide layer 7 on the active areas.
Subsequently, polysilicon is deposited over the entire surface of the resultant semiconductor structure by using the chemical vapor deposition, and a polysilicon layer is formed on the silicon oxide layer 7. Silicon oxide is deposited to 250 nanometers thick over the entire surface of the polysilicon layer by using the chemical vapor deposition, and a silicon oxide layer is laminated on the polysilicon layer. A photo-resist etching mask (not shown) is patterned on the silicon oxide layer, and has striped masking portions extending in the perpendicular direction to the striped impurity regions 2a/2b. Using the photo-resist etching mask, the silicon oxide layer and the polysilicon layer are selectively etched away, and composite gate electrodes 8 and upper insulating layers 9 as shown in FIG. 1D.
The composite gate electrode partially serves as control gate electrodes 10 of the stacked gate type memory transistors and partially as selecting gate electrodes 11 of the associated field effect transistors. Accordingly, the silicon oxide layers 6/7 under the control gate electrodes serve as upper gate oxide layers of the stacked gate type memory transistors, and the silicon oxide layers 6/7 under the selecting gate electrodes serve as gate oxide layers of the associated field effect transistors.
Subsequently, silicon oxide is deposited to 100 nanometers thick over the entire surface of the resultant semiconductor structure, and the silicon oxide layer is anisotropically etched without any etching mask. Side walls 12 are left on the side surfaces of the control gate electrodes 10 and the selecting gate electrodes 11. The silicon oxide layers 6/7 are exposed to gaps between the side walls 12. The silicon oxide layers 6/7 and the floating gate electrodes exposed to the gaps are etched away, and the isolating oxide layer 3 and side surfaces of the floating gate electrodes 5 are exposed to the gaps. Easing gate oxide layers 13 are grown to 20 nanometers thick on the side surfaces of the floating gate electrodes 5.
Polysilicon is deposited over the entire surface of the resultant semiconductor structure. The polysilicon fills the gaps between the side walls 12, and a polysilicon layer is spread over the silicon oxide layer 9. Using a photo-resist etching mask, the polysilicon layer is patterned into erasing gate electrodes 14, and the erasing gate electrodes 14 are held in contact with the erasing gate oxide layers 13 as shown in FIG. 1E. The erasing gate electrodes 14 occupy every other gaps between the side walls 12.
Though not shown in the drawings, the resultant semiconductor structure is covered with an inter-level insulating layer, and conductive lines are formed on the inter-level insulating layer in such a manner as to be connected through contact holes in the inter-level insulating layer to appropriate conductive portions.
In order to increase the data storing capacity of the prior art semiconductor non-volatile memory device, it is necessary to scale down the split gate type memory cell. This means that both of the stacked gate type memory transistor and the selecting transistor are scaled down. When the selecting transistor is scaled down, it is appropriate to decrease the threshold of the selecting transistor, and the manufacturer makes the silicon oxide layers 6/7 under the selecting gate electrode 11 thinner. Although the silicon oxide layers 6/7 between the floating gate electrode 5 and the control gate electrode 10 is half as thick again as the silicon oxide layers 6/7 under the selecting gate electrode 11, the silicon oxide layers 6/7 between the floating gate electrode 5 and the control gate electrode 10 also becomes thinner, because the silicon oxide layers 6/7 are concurrently deposited for those purposes. However, such thin silicon oxide layers 6/7 between the floating gate electrode 5 and the control gate electrode 10 allow a large amount of leakage current to flow through the silicon oxide layers 6/7 between the floating gate electrode 5 and the control gate electrode 10. Thus, the reduction of the thickness results in low reliability of stacked gate type memory transistor.
Japanese Patent Publication of Unexamined Application No. 8-204034 discloses a process for fabricating a split gate type memory cell where the insulating layer between the floating gate electrode and the control gate electrode and the gate oxide layer under the selecting gate electrode are independently grown. According to the Japanese Patent Publication of Unexamined Application, a polysilicon layer over a silicon substrate is selectively oxidized by using the LOCOS (local oxidation of silicon) technique, and the silicon oxide forms a thick control gate oxide layer. Sharp edges take place at both sides of the control gate oxide layer due to the bird""s beaks during the LOCOS, and, accordingly, the floating gate electrode is sharpened at both sides of the upper portion. Using the thick control gate oxide layer as an etching mask, the polysilicon layer is patterned into a floating gate electrode. Side walls are formed on side surfaces of the floating gate electrode, and the silicon substrate is exposed on both sides of the side walls. The resultant semiconductor structure is covered with silicon oxide layers, and the silicon oxide layers serve as a gate oxide layer for a selecting transistor on the silicon substrate. A control gate electrode is patterned on the silicon oxide layers in such a manner as to be partially overlapped with the floating gate electrode. Finally, dopant impurity is ion implanted into the silicon substrate in self-aligned manner with the control gate electrode and the side wall. The sharp edges of the floating gate electrode are desirable for evacuation of accumulating electron from the floating gate electrode to the control gate electrode, because tunneling current is much liable to flow from the sharp edges.
The control gate oxide layer and the gate oxide layer for the selecting transistor are independently grown, and the manufacturer appropriately determines the thickness of the control gate oxide layer and the thickness of the gate oxide layer of the selecting transistor. However, the prior art process disclosed in the Japanese Patent Publication of Unexamined Application is hardly applied to the prior art process shown in FIGS. 1A to 1E.
The first reason is the location of the control gate electrode. The control gate is opposed to the sharp edge or the bird""s beak produced through the LOCOS process. The sharp edge aims at the easy initiation of tunneling current during the erasing operation, and the control gate electrode is expected to extend over the sharp edge of the floating gate electrode. For this reason, the control gate electrode is patterned on the side wall, and both ends of the control gate electrode are on the gate oxide layer of the selecting transistor and on the control gate oxide layer over the upper surface of the floating gate electrode. The source/drain regions has to be formed after the patterning of the control gate electrode in order to be self-aligned with the control gate electrode. On the other hand, the prior art process shown in FIGS. 1A to 1E has a premise that the striped impurity regions 2a/2b are partially overlapped with the floating gate electrode 5. The source/drain regions self-aligned with the control gate electrode consumes wide real estate, and is not desirable for a large data storage capacity.
The second reason is undesirable prolongation of the etching for exposing the side surfaces of the floating gate electrode 5. As described hereinbefore, the prior art split gate type memory cell requires the erasing electrode 14, and the erasing electrode 14 is opposed to the side surface of the floating gate electrode 5 through the erasing gate oxide layer 13. If the floating gate electrode 5 is covered with a thick silicon oxide grown through the LOCOS, the etching consumes long time until the side surfaces are exposed. Thus, the thick silicon oxide layer grown through the LOCOS reduces the throughput of the etching system.
The third reason is non-uniform erasing gate oxide layer 13. The oxidation tends to proceed at high speed immediately under the control gate oxide layer 6/7. The easing gate oxide layer 13 is thick in the vicinity of the control gate electrode 6/7 and the isolating layer 3 and thin therebetween as shown in FIG. 2. The non-uniform erasing gate oxide layer 13 makes the erasing characteristics unstable, and the thick silicon oxide layer grown through the LOCOS is undesirable.
Thus, the prior art process disclosed in the Japanese Patent Publication of Unexamined Application is featured by the bird""s beak opposed to the control gate, and is less combined to the prior art process shown in FIGS. 1A to 1E.
It is therefore an important object of the present invention to provide a semiconductor non-volatile memory device, the sprit gate type memory cell of white has a control gate insulating layer and a selecting gate insulating layer both having respective appropriate thickness.
It is also an important object of the present invention to provide a process for fabricating the sprit gate type memory cell.
To accomplish the object, the present invention proposes to form a part of a control gate insulating layer of silicon nitride.
In accordance with one aspect of the present invention, there is provided a semiconductor non-volatile memory device having a split gate type memory cell assigned to an active region on a semiconductor substrate, the split gate type memory cell, and the split gate type memory cell comprises a stacked gate type memory transistor including a first impurity region formed in a first sub-region of the active region, a first gate insulating layer covering a part of the first impurity region and a second sub-region of the active region adjacent to the first sub-region, a floating gate electrode formed on the first gate insulating layer, a second gate insulating layer having a first thickness and including a first insulating sub-layer formed of a first insulating material on an upper surface of the floating gate electrode and a second insulating sub-layer formed of silicon nitride on the first insulating sub-layer and a control gate electrode formed on the second gate insulating layer, and a selecting transistor including a second impurity region formed in a third sub-region of the active region spaced from the second sub-region, a third gate insulating layer having a second thickness less than the first thickness and formed of a second insulating material on at least a fourth sub-region of the active region between the third sub-region and the second sub-region and a selecting gate electrode connected to the control electrode and formed on the third gate insulating layer.
In accordance with another aspect of the present invention, there is provided a process for fabricating a split gate type memory cell on an active region of a semiconductor substrate, and the process comprises the steps of forming a first impurity region and a second impurity region spaced from each other in the active region, covering a part of the first impurity region and a sub-region of the active region adjacent to the first impurity region with a first gate insulating layer, successively depositing a first conductive material, a first insulating material and silicon nitride for forming a first conductive material layer, a first insulating material layer and a silicon nitride layer on the first gate insulating layer, patterning the first conductive material layer, the first insulating material layer and the silicon nitride layer into a first conductive stripe, a first insulating sub-layer laminated on the first conductive stripe and a second insulating sub-layer laminated on the first insulating sub-layer, covering the second insulating sub-layer and another sub-region of the active region adjacent to the sub-region with a second insulating layer of a second insulating material for forming a second gate insulating layer on the first conductive stripe and a third gate insulating layer on the another subregion, forming a second conductive stripe of a second conductive material extending over the second gate insulating layer and the third gate insulating layer for providing a control gate electrode on the second gate insulating layer and a selecting gate electrode on the third gate insulating layer, and selectively etching the first conductive stripe for forming a floating gate electrode between the first gate insulating layer and the second gate insulating layer.